==Question 1: Suppose our datapath is only 4 bits, rather than 32 (we are doing this so that the question doesn't involve too much busywork). Suppose we are executing add $t0,$t1,$t2, and that $t1 = 0b0011 and $t2 = 0b0001. What values do the following have? Ainvert 0 Binvert 0 Operation 2 (or 0b10) CarryIn to ALU0 0 a0 1 b0 1 Output of the adder of ALU0 0 CarryOut of ALU0 1 Result0 0 a1 1 b1 0 Output of the adder of ALU1 0 CarryOut of ALU1 1 Result1 0 a2 0 b2 0 Output of the adder of ALU2 1 CarryOut of ALU2 0 Result2 1 a3 0 b3 0 Output of the adder of ALU3 0 CarryOut of ALU3 0 Result3 0 Zero 0 Set 0 ==Question 2: Suppose we are executing sub $t0,$t1,$t2, and that $t1 = 0b0011 and $t2 = 0b0100. What values do the following have? Ainvert 0 Binvert 1 Operation 2 CarryIn to ALU0 1 a0 1 b0 0 Output of the adder of ALU0 1 CarryOut of ALU0 1 Result0 1 a1 1 b1 0 Output of the adder of ALU1 1 CarryOut of ALU1 1 Result1 1 a2 0 b2 1 Output of the adder of ALU2 1 CarryOut of ALU2 0 Result2 1 a3 0 b3 0 Output of the adder of ALU3 1 CarryOut of ALU3 0 Result3 1 Zero 0 Set 1 == Question 3 Suppose we are executing slt $t0,$t1,$t2, and that $t1 = 0b0011 and $t2 = 0b0101. What values do the following have? Here's the operation that is carried out: 0 0 1 1 1 <-- carries 0 0 1 1 1 0 1 0 ------- 1 1 1 0 Ainvert 0 Binvert 1 Operation 3 CarryIn to ALU0 1 a0 1 b0 1 Output of the adder of ALU0 0 CarryOut of ALU0 1 Result0 1 a1 1 b1 0 Output of the adder of ALU1 1 CarryOut of ALU1 1 Result1 0 a2 0 b2 1 Output of the adder of ALU2 1 CarryOut of ALU2 0 Result2 0 a3 0 b3 0 Output of the adder of ALU3 1 CarryOut of ALU3 0 Result3 0 Zero 0 Set 1 == Question 4 When we looked at SLT in our construction of the ALU, the destination register ($t0 in the example above) was set depending only on whether the result of the subtraction is negative (i.e., the Set output of ALU31). But this isn't, in general, sufficient. Suppose our datapath is 4 bits, and we execute: slt $t0,$t1,$t2 where $t1 = -7dec = 0b1001 $t2 = 6dec = 0b0110 What value would $t0 be set to? Here is what would happen: a3,a2,a1,a0 in the diagrams is 1001 ($t1) b3,b2,b1,b0 in the diagrams is 0110 ($t2) -7 would be added to -6. In binary: 1001 + 1010 ------ 0011 Thus, the Set of the 4-bit ALU will be 0, since the result is positive (and the most significant bit of the sum is 0). And, $t0 would be set to 0. This is wrong! -7 IS less than 6. Putting a 0 into $t0 means that the first number is NOT smaller than the second one. What's going on? Overflow! The smallest negative number that fits in N bits is -2E(N-1). In our case, this value is -2E(3) = -8. The actual sum, -13, does not fit. So, the hardware is not as simple as shown in the figure. Instead, the "less" into to ALU0 is the result of the following: overflow and set' or set and overflow' That is, less0 is the same as set if there is no overflow, and the complement of set if there is overflow. What is overflow in the case of subtraction? Remember: signed overflow occurs when the sign of the result is incorrect. There are two cases, for subtraction: a31 b31' s' + a31' b31 s31 That is: neg - pos (so neg + neg) and the result is pos pos - neg (so pos + pos) and the result is neg