Question 1: Suppose that a lw instruction is executed using the
multi-cycle control shown in Figure 5.28.  State what happens during
each cycle of execution. Your answers should be in terms of A, B,
ALUOut, PC, Memory[...], IR[...], Reg[...], sign-extend, MDR, PC,
etc. as in the lecture notes.  Though you have this answer in your
lecture notes, do this just by looking at Figure 5.28.  You can check
your answers against the lecture notes later.

cycle 1:

IR <= Memory[PC]
PC = PC + 4

cycle 2:
A <= Reg[IR[25:21]]
B <= Reg[IR[20:16]]
ALUOut <= PC + sign-exend(IR[15:0] << 2)

cycle 3:
ALUOut <= A + sign-exgtend(IR[15:0])

cycle 4:
MDR < = Memory[ALUOut]

cycle 5:
Reg[IR[20:16]] <= MDR 


Question 2: Suppose that a lw instruction is executed using the multi-cycle
control shown in Figure 5.28.  What are the values of ALUSrcA,
ALUSrcB, IorD and MemToReg during each cycle?  Please fill in the
table below.  (Use X for ``don't care''.)  Please do this looking only
at Figure 5.28.  You can check your answers against the lecture notes
later.  


                ALUSrcA        ALUSrcB        IorD                          MemToReg

Cycle 1        0 (the PC)       1 (the 4)       0 (addr from PC)                X

Cycle 2        0 (the PC)       3               X (no memory access)            X
                             (sign-extended 
                              shifted imm value)

Cycle 3        1 (rs)           2               X (no memory access)            X
                             (sign-extended imm)

Cycle 4        X                X              1 (address from ALUout)          X

Cycle 5        X                X              X                                1 


Question 3: This question is about the components of the multi-cycle
datapath that deal with updates to the PC.  Again, answer this
question by looking at Figure 5.28.

Suppose that the current instruction is an add instruction.  During
which cycle is PCWrite 1?  

   Cycle 1, when the PC is updated to PC + 4

During that cycle, what values do the following signals have?

ALUSrcA  0

ALUSrcB  1

PCSource 0

Now suppose the current instruction is a beq, and that the two
registers are equal (so, the branch will be performed).

During cycle 3, what values do the following have?

PCSource  01

Output of the AND gate at the top left  1 (PCWriteCond is 2 and
    zero output of ALU is 1)

Output of the OR gate at the top left  1 since the output of the AND
  gate is 1

Now suppose that the current instruction is a j.

During cycle 3, what values do the following have:

PCWrite  1

PCSource 10