Given Figures 5.16 and 5.17, specify the settings of the control
signals for the instruction:  beq $t0,$t1,label

Note: the bottom of page 305 states that the 9 control signals shown
in Figure 5.17 are the ones listed in Figure 5.16 + ALUop1 and ALUop0.
However, there is an error.  Figure 5.17 includes the signal "branch"
(which is correct), while Figure 5.16 lists "PCSrc" instead, which is
a holdover from Figure 5.15 (we replaced PCSrc with the and-gate).

On the exam, if a bit is X (doesn't matter), that will need to be
indicated.  

Since ALUop1 and ALUop2 were not in the second figure, I didn't take a
point off for excluding it.  If someone got everything right, their
grade is 5.7 / 5.0

Figure 5.17:

  RegDest = X doesn't matter  
  Branch = 1  This is PCSrc in Figure 5.16.
  MemRead = 0
  MemtoReg = X  doesn't matter, since RegWrite is 0
  ALUop1, ALUop2 = the op for sub (which is 01, but that wasn't supplied)
  MemWrite = 0
  ALUSrc = 0
  RegWrite = 0 


Figure 5.16:
  RegDest = X doesn't matter  
  RegWrite = 0 
  ALUSrc = 0
  PCSrc = 1  if this were a control signal to the MUX, it's value would be 1
  MemRead = 0
  MemWrite = 0
  MemtoReg = X  doesn't matter, since RegWrite is 0
  
ALUop1, ALUop2: the op for sub (which is 01, but that wasn't supplied)