COE
1502
ADVANCED DIGITAL DESIGN
Fall 2006/2007
Mondays and Wednesdays from 1:00PM to 2:50PM
367 Benedum Hall
Instructors
Rami Melhem (melhem@cs.pitt.edu)
phone: 624-8493
Office Hours: By appointment
Teaching assistants
Sam Dickerson (sdickerson@ee.pitt.edu)
271-I Benedum Hall
Arnaldo Noyola (ajnoyola@cs.pitt.edu)
Purpose:
Learn tools and techniques of modern digital design for large scale digital systems. This course complements the Computer Architecture Course (CoE 1541) with actual design experience for the processor covered in that course.
Requirements and grading:
Self tutorial (5%)
Project 1 (35%): testbench simulation and synthesis of muticycle CPU.
Project 2 (30%): testbench simulation of pipelined CPU
Final exam (30%).
Academic integrity policy
Academic dishonesty in any form will not be tolrated. Academic dishonesty includes plagiarism of programs, homework solutions, papers, reports, exams or any material turned in for course credit. Academic dishonesty cases will result in loss of credit and referal to the university disciplinary authorities.
Note for disable students
If you have a disability for which
you are or may be requesting an accomodation, you are encouraged to contact the
Office of Disability Resources and Services, 216 William Pitt
Course account and Lab partner policy
You have already been issued a course network account. It is YOUR
responsibility to ensure that you can successfully log into your account
throughout this term. Inability to logon to your network account is not the
instructor?s responsibility, and must be handled with the Computer Engineering
technical support staff. This is an extremely important consideration for the
final exam period!
Your design data is backed up by the technical support staff on a nightly basis
(M-F). However, you are responsible for your data. We recommend that you make
your own backups using zip disks, floppy disks, flash drives, or FTP. We will
not grant extensions due to loss of data!
For the projects, you will work in groups. You MUST choose your lab partner
wisely. A lab partner who is not doing his/her fair share of the work is NOT an
acceptable excuse for late or incomplete work under ANY circumstances. No
partial credit or special allowance will be given for this type of situation.
Reference information
Simulator
Quick Reference Sheet
Open
Verification Library Documentation
"Wild-One"
Board Reference Manual
MIPS
Instruction Types
MIPS
Instruction Set Detail
HP
1600 LogicAnalyzer
Using
the logic Analyzer
Example
final exam
Course schedule, assignments and lecture slides
Group Registration
Individual Registration
Department
of Computer Science University
of Pittsburgh