Below is a procedure for uploading a custom program into the memory_1502. Technically, we're not uploading the program so much as we're really generating pre-loaded VHDL of an SRAM (scsp_sram64_arch.vhd). This SRAM is embedded in the memory_1502 module. This procedure is FYI only and available for those interested in constructing simple programs to test their pipelined CPUs with exceptions and memory interface.
If you so choose to generate your own MIPS assembly program via SPIM and "upload" that program into the memory_1502, follow the steps below.
As part of the final project, you must demonstrate execution of simpletest (simpletest64.lst, simpletest64.s, and simpletest64.bin).
1) Copy the memory_1502 and all its subcomponents from COELib to a library you can write to. Afterwards, in your memory_1502 module, remap each subcomponent library from COELib to the library you designated.
2) Generate your own assembly program via SPIM. Afterwards, you'll have to modify the listing and save the file as a *.bin. The file needs to be in the format similar to simpletest64_ex.bin (availabe on the course website).
3) Open the Host Applicaiton V2 located at I:\1502\Wid-Star Host App v2
4) In the Memory file field, browse for your custom *.bin file and then press the Generate Memory button.
5) The host application should have generated a scsp_sram64_arch.vhd file in the same folder as your custom *.bin file.
6) Open up your copy (in your writable library) of the scsp_sram64 module and copy/paste the scsp_sram64_arch.vhd file generated by the host application into the scsp_sram64.
If all goes well, you should have a fully-synthesizable, pre-programmed, readable and writable memory_1502.
Additional
Benchmark Program
See the page explaining the final project