Publications
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Taecheol Oh, Kiyeon Lee, and Sangyeun Cho,
An Analytical Performance Model for Co-Management of Last-Level Cache and Bandwidth Sharing,
Proceedings of the IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS),
Singapore, July 2011.
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Kiyeon Lee and Sangyeun Cho,
In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces,
Proceedings of the IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS),
Singapore, July 2011.
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Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, and Sangyeun Cho,
Two-Phase Trace-driven Simulation (TPTS): A fast multicore processor architecture simulation approach,
Software: Practice and Experience (SPE), 40(3):239~258, March 2010.
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Taecheol Oh, Hyunjin Lee, Kiyeon Lee, and Sangyeun Cho,
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor,
Proceedings of the IEEE Computer Society Symposium on VLSI (ISVLSI),
Tampa, Florida, May 2009.
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Kiyeon Lee, Shayne Evans, and Sangyeun Cho,
Accurately Approximating Superscalar Processor Performance from Traces,
Proceedings of the IEEE Int'l Symposium on Performance Analysis of Systems and Software (ISPASS),
Boston, Massachusetts, April 2009.
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Sangyeun Cho, Socrates F. Demetriades, Shayne V. Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, and Michael Moeng,
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation,
Proceedings of the Int'l Conference on Parallel Processing (ICPP),
Portland, Oregon, September 2008.
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Sangyeun Cho, Lei Jin, and Kiyeon Lee,
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems,
Proceedings of the IEEE Int'l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA),
Daegu, Korea, August 2007. Invited paper.
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