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Sep, 2000-Jun, 2004
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Undergraduate in
Department
of Compter Science and Engineering,
Zhejiang
University, China |
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Sep, 2000-Jun, 2004 |
Student in Experimental Honor Class,
Chu Kezhen Honors
College, Zhejiang University, China |
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Sep, 2004 - Present |
Graduate Student at Computer Science, University of
Pittsburgh |
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Publications: |
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Lei Jin and Sangyeun Cho, SOS:
A Software-Oriented Distributed Shared Cache Management Approach
for Chip Multiprocessors, Proceedings of the Int'l
Conference on Parallel Architectures and Compilation Techniques
(PACT), Raleigh, North Carolina, September 2009, to appear. |
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Lei Jin and Sangyeun Cho.
Taming Single-Thread Program Performance on Many Distributed
On-Chip L2 Caches, Proceedings of the International
Conference on Parallel Processing (ICPP), Portland, OR,
September 2008. |
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Sangyeun Cho, Socrates F.
Demetriades, Shayne V. Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee,
and Michael Moeng.
TPTS: A Novel Framework for Very Fast Manycore Processor
Simulation, Proceedings of the International
Conference on Parallel Processing (ICPP), Portland, OR,
September 2008. |
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Sangyeun Cho, Lei Jin, and
Kiyeon Lee,
Achieving Predictable Performance with On-Chip Shared L2
Caches for Manycore-Based Real-Time Systems,
Proceedings of the IEEE Int'l Conference on Embedded and
Real-Time Computing Systems and Applications (RTCSA), Daegu,
Korea, August 2007. Invited paper.
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Lei Jin and Sangyeun Cho,
Better than the Two: Exceeding
Private and Shared Caches via Two-Dimensional Page Coloring,
Proceedings of the Workshop on Chip Multiprocessor Memory Systems
and Interconnects (CMP-MSI), during the IEEE Int'l Symposium on
High-Performance Computer Architectures (HPCA), Phoenix,
Arizona, February 2007. |
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Sangyeun Cho and Lei Jin,
Managing Distributed, Shared L2 Caches through OS-Level Page
Allocation , Proceedings of the IEEE/ACM Int'l Symposium
on Microarchitecture (MICRO), Orlando, Florida, December 2006
Nominated for the best paper award |
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Lei Jin, Hyunjin Lee, and
Sangyeun Cho,
A Flexible Data to L2
Cache Mapping Approach for Future Multicore Processors, Proceedings of the ACM Workshop on Memory Systems Performance and
Correctness (MSPC) during ACM Int'l Conference on
Architectural Support for Programming Languages and Operating
Systems (ASPLOS), San Jose, CA, October 2006 |
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Lei Jin and Sangyeun Cho,
Reducing Cache Traffic and Energy
with Macro Data Load, Proceedings of the ACM Int'l
Symposium on Low Power Electronics and Design (ISLPED),
Tergernsee, Germany, October 2006 |
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Lei Jin and Sangyeun Cho,
A Characterization Study on Memory
Value Reuse, Proceedings of the Workshop on Memory
Performance Issues (WMPI) during IEEE Int'l Symposium on
High-Performance Computer Architectures (HPCA), Austin, Texas,
February 2006 |
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Technical Report: |
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Lei Jin and Sangyeun Cho, TR-08-160,
Department of Computer Science, University of Pittsburgh,
November, 2008. |
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