# # A simple diagnostic that will execute most instructions # at least once and them dump the register file so that you # can see it on the memory output bus # main: j start # exception vector j exception j exception j exception j exception start: # Initialize the status register addi $2, $0, 0x0006 addi $2, $0, 0x0001 mtc0 $12, $2 # Try modifying R0 addi $0, $0, 1 # R0 had better still be 0 # # misc ALU tests # addsub sub $24, $0, $0 # r24 = 0 addi $2, $0, 1 # r2=1 addi $3, $0, -1 # r3=-1 add $4, $3, $2 # r4=0 (no exceptions) andi $5, $3, 255 # r5=255 =0x00000000_000000FF addu $6, $5, $2 # r6=256 =0x00000000_00000100 addiu $7, $6, 768 # r7=1024 =0x00000000_00000400 subu $8, $7, $6 # r8=768 =0x00000000_00000300 # logic ori $9, $0, 21845 # r9=21845 =0x00000000_00005555 or $9, $9, $0 # r9=21845 =0x00000000_00005555 =unchanged and $9, $9, $3 # r9=21845 =0x00000000_00005555 =unchanged nor $10, $9, $0 # r10=-21846 =0xFFFFFFFF_FFFFAAAA xor $11, $10, $10 # r11=0 =0x00000000_00000000 xori $12, $9, -13 # r12=-21850 =0xFFFFFFFF_FFFFAAA6 #shift sll $13, $9, 8 # r13=5592320 =0x00000000_00555500 sllv $14, $2, $2 # r14=2 =0x00000000_00000002 srl $15, $10, 5 # r15=134217045=0x00000000_07fffD55 srlv $16, $9, $2 # r16=10922 =0x00000000_00002AAA sra $17, $3, 4 # r17=-1 =0xFFFFFFFF_FFFFFFFF srav $18, $9, $14 # r18=5461 =0x00000000_00001555 slt $19, $9, $9 # r19=0 =0x00000000_00000000 slt $20, $5, $6 # r20=0 =0x00000000_00000001 sltu $21, $4, $3 # r21=1 =0x00000000_00000001 sltiu $22, $3, 0 # r22=0 =0x00000000_00000000 # test the jump instructions addi $23,$0,0 # set register 23 to zero j jumpok addi $23,$0,-1 # -1 in r23 means jump failed jumpok: addi $24,$0,0 # initialize register 24 to zero jal jalok # this is taken w/$31 = PC addi $24,$24,1 # should not come here after jal, but will after jalr below j out # jalok: addi $24,$0,100 # re-init $24 to 100 jalr $31 # now jump back 3 instructions out: # will test jr below ## branch instructions ## for these test r2 = 1, r3 = -1 (see above) beq $3,$3 taken # taken branch: PC moves ahead by 8 stuck: j stuck # don't execute this instruction taken: beq $3, $2, stuck # no take branch (failures get stuck) bne $3,$2 taken1 # taken branch: PC moves ahead by 8 stuck1: j stuck1 # don't execute this instruction taken1: bne $3, $3, stuck1 # no take branch (failures get stuck) bltz $3, taken2 # taken branch: PC moves ahead by 8 stuck2: j stuck2 # don't execute this instruction taken2: bltz $2, stuck1 # no take branch (failures get stuk) blez $0, taken3 # taken branch: PC moves ahead by 8 stuck3: j stuck3 # don't execute this instruction taken3: blez $2, stuck3 # no take branch (failures get stuck) blez $3, taken4 # taken branch: PC moves ahead by 8 stuck4: j stuck4 # don't execute this instruction taken4: blez $2, stuck4 # no take branch (failures get stuck) bltzal $3, taken5 # taken branch: PC moves ahead by 8 stuck5: j stuck6 # don't execute this instruction taken5: bltzal $2, stuck5 # no take branch (failures get stuck); add $25,$0,$31 # link address in r25 bgtz $2, taken6 # taken branch: PC moves ahead by 8 stuck6: j stuck6 # don't execute this instruction taken6: bgtz $3, stuck6 # no take branch (failures get stuck) bgez $0, taken7 # taken branch: PC moves ahead by 8 stuck7: j stuck7 # don't execute this instruction taken7: bgez $3, stuck7 # no take branch (failures get stuck) bgez $2, taken8 # taken branch: PC moves ahead by 8 stuck8: j stuck8 # don't execute this instruction taken8: bgez $3, stuck8 # no take branch (failures get stuck) bgezal $2, taken9 # taken branch: PC moves ahead by 8 stuck9: j stuck9 # don't execute this instruction taken9: bgezal $3, stuck9 # no take branch (failures get stuck); add $26,$0,$31 # link address in r26 # test load/store (some of them at least) sw $17, 640($0) sb $0, 644($0) lw $25, 640($0) # r25 = 0xffffff00_ffffffff lhu $26, 640($0) # r26 = 0x00000000_0000ffff lbu $27, 640($0) # r26 = 0x00000000_000000ff addi $28, $0, 704 # r28 = 000002c0 (see section below addi $28, $28, 0 # # this is your output.. sw $2, 0($28) addi $28,$28,0x10 sw $3, 0($28) addi $28,$28,0x10 sw $4, 0($28) addi $28,$28,0x10 sw $5, 0($28) addi $28,$28,0x10 sw $6, 0($28) addi $28,$28,0x10 sw $7, 0($28) addi $28,$28,0x10 sw $8, 0($28) addi $28,$28,0x10 sw $9, 0($28) addi $28,$28,0x10 sw $10, 0($28) addi $28,$28,0x10 sw $11, 0($28) addi $28,$28,0x10 sw $12, 0($28) addi $28,$28,0x10 sw $13, 0($28) addi $28,$28,0x10 sw $14, 0($28) addi $28,$28,0x10 sw $15, 0($28) addi $28,$28,0x10 sw $16, 0($28) addi $28,$28,0x10 sw $17, 0($28) addi $28,$28,0x10 sw $18, 0($28) addi $28,$28,0x10 sw $19, 0($28) addi $28,$28,0x10 sw $20, 0($28) addi $28,$28,0x10 sw $21, 0($28) addi $28,$28,0x10 sw $22, 0($28) addi $28,$28,0x10 sw $23, 0($28) addi $28,$28,0x10 sw $24, 0($28) addi $28,$28,0x10 sw $25, 0($28) addi $28,$28,0x10 sw $26, 0($28) addi $28,$28,0x10 sw $27, 0($28) addi $28,$28,0x10 sw $28, 0($28) addi $28,$28,0x10 sw $29, 0($28) addi $28,$28,0x10 sw $30, 0($28) add $31,$0,$0 jr $31 j 1