Unit 2

Synthesizing the ALU

Synthesis Concepts

You have now designed and simulated an ALU for the MIPS architecture in VHDL using the FPGA Advantage and ModelSim tools in HDL Designer. The VHDL source code, however, does not contain the information necessary to directly implement the desired device in hardware, whether it be in a reconfigurable device such as an FPGA or in a custom ASIC.

In this class we wish to implement our designs in Xilinx brand FPGA's from the XC2VP100 family. These devices have a particular structure, consisting of Combinational Logic Blocks (CLBs), interconnect, and Input/Output Blocks (IOBs). Our VHDL description of the behavior of the desired device must be translated into a netlist file of logic which can be mapped into CLBs, IOBs and interconnect by Xilinx tools.

The process of taking VHDL source and creating a logic netlist is called Synthesis. The Xilinx synthesis tool is XST (Xilinx Synthesis Tool), which will take your VHDL source code and sythesize it into logic, outputting an NGC netlist file.

Copying the ALU Wrpper Design Unit

Before we even begin to think about synthesizing the ALU, there is one other step we must consider concerning the particular platform which we be implementing the design on. The hardware which we will be using to implement our designs is a reconfigurable computing board called a Wild-Star II Pro board which is made by a company called Annapolis Microsystems. The Wild-Star board consists of a user configurable Xilinx Virtex-II PRO FPGAs which are referred to as processing elements (PE), as well as DRAM memory, a PCI interface, and connectors which we can use to interface to the logic analyzers.

Due to the fact that the FPGA's are soldered onto the board with predefined I/O connections, it is necessary to have a framework around our logic design which sets up the interface to the rest of the Wild-Star card. The external framework will be given to you as a pre-synthesized netlist which will be merged with your design when it is fed to the Xilinx tools which place and route the logic into a binary file that can be uploaded to configure the FPGA.

In addition to the interface framework, however, it is also necessary to create logic for this ALU test which will handle communication with the PCI bus so that test data can be uploaded from the host and results can be returned. A "wrapper" design unit has been created which will perform these tasks and interface directly with your ALU design.

The wrapper design is called wrapper and a copy has been placed into the COELib design library where your ADD64 design unit is located. Since this library is read-only for the class, you will need to make a copy of the wrapper and its sub components into your ALU library. It has been created so that it can be copied from one library to another without creating any problems with incorrect library references. You must, however, make sure that your ALU design has been created with the library correctly named ALU in all capital letters. Although VHDL is not case sensitive, FPGA Advantage is in certain cases.

To copy the wrapper design unit from the COELib library to the ALU library, first open both libraries in the Design Browser window. In the Project tab, expand the COELib library tree and select the wrapper design unit. Go to the Edit menu and click on Copy. Now open the ALU library and select Paste from the Edit menu to copy the design unit.  Repeat these steps for the input_interface ,Output_interface, memory_loader and lad_control design units.

On the right hand side of the design, you will notice an embedded (yellow) block named "LOGIC_ANALYZER_SIGNALS". This block will constitute your interface to the logic analyzer. There are three busses assigned in this block (to a default values), ioconn_out0, ioconn_out1, and ioconn_out2. These busses represent each of the outputs that can connect pins on the FPGA to a logic analyzer. Each connection consists of 32 signals, for a total of 96 possible output signals. You are responsible for connecting signals in the ALU Wrapper to these busses so that you can examine the operation of your design on the analyzer. To do this, change the contents of this embedded block such that certain ranges of bits within each of these busses are assigned to values within your design. For example, the following VHDL statement will assign the low-order 8 bits of A to bits 15 down to 8 on the ioconn0 connector: 

 
  ioconn_out0(15 downto 8) <= A(7 downto 0);

The recommended initial configuration for these signals is as follows:

ALU Inside of FPGA Wrapper

 

Before moving on, check to make sure that everything is OK with the copied design unit by opening it up and then attempting to open some of the components, especially the ALU.

Using HDL Designer to perform Synthesis

Now we are ready to get started. First, in the Design Manager, open the "Tasks and Templates" frame by selecting View | SubWindows | Tasks and Templates.

Select the wrapper in the Design Browser and double-click the Xilinx Synthesis Tool Flow in the Tasks and Templates frame.

At this point, you will see the following window. Select 200 as the speed. Next, click the Advanced button.

In this window, change the Optimization Mode to "Speed" and the Optimization Level to "High". Now, click the "FPGA Specific" tab.

In this window, turn off the option "Add I/O Buffers". Then click OK on this window, and OK on the "Synthesis Setup" window.

XST will take a few minutes to completely run. During this process, XST does three things. First, it takes the VHDL that was generated by FPGA Advantage and breaks it down into a list of inter-connected logic gates. Then it attempts to perform logic minimization; attempting to remove as much redundant logic as necessary to conserve space on the FPGA. Finally XST takes the optimized netlist and builds the final output against the features that are provided by the FPGA we are using, in this case the Xilinx Virtex-II Pro (2vp100ff1704-5) on the Wild-Star board. Most of the output messages that XST generates can be ignored but you may want to scroll through the text to see some of what XST does. In particular you may want to find where XST gives an area and timing report. This gives us an idea how much of the logic capability of the FPGA we are using, for the ALU it should not be very much.

·  Now go on to Mapping, Placing, and Routing the Design.