Unit 2b

Mapping, Placing and Routing the ALU Design

Now that you have synthesized the design, it is time to combine it with the interface logic, map it into the Xilinx Virtex-II Pro architecture, and place and route it.

First, open the Xilinx ISE 7.1i tool. You will be presented with a "Tip of the Day". Uncheck the "Show Tips at Startup" option and click OK.

You will now be presented with ISE's main window.

We want to create a new project, so select File | New Project. Name the project whatever you wish and select a path in your home directory. Change the "Top-Level Module Type" to "NGC/NGO" and click Next.

Set the input design by browsing to I:\1502\PE0 and selecting pe.ngc. Click Next.

The next window allows you to set the FPGA device settings, however the current settings were read from the netlist file and are therefore correct. Click Next.

This window provides a summary of the project. Click Finish.

You will now be returned to the ISE project window. Before we proceed, you need to copy your synthesized wrapper netlist into the Xilinx ISE project directory. The wrapper netlist is located under your project directory in the XST downstream directory for the ALU library. This directory is located at: "H:\ALU\ise\wrapper_struct" and the filename is wrapper.ngc. Copy this file to the directory that you selected for the Xilinx ISE project (i.e. "H:\alu_synth").

Before we can perform the place-and-route, we need to make a change to one of the flow settings. In the Processes frame, expand the "Implement Design" item, right-click on "Map", and click "Settings."

In the settings window, change the "Property display level" to "Advanced". Next, turn on "Allow Logic Optimization Across Hierarchy". Then click OK on this window.

We are now ready to place-and-route the design. In the Processes frame, right-click on "Generate Programming File" and click on "Run". The place-and-route will run, taking a few minutes. You'll know when the process is complete when you see "Process 'Generate Programming File' is up to date." at the bottom of the ISE window.

The result of this process is a BIT file. This file must be converted to a BIN file before it can be loaded onto the FPGA. To perform this conversion, open a command window (Start | Run | "cmd"). Change the drive to I: (type "I:"), and change directory to your ISE project directory (for example, type: "cd \alpha\alu_synth"). Next, type: "promgen -u 0 pe.bit -p bin -w".

Now that you have a valid BIN image of your design, you are ready to Run your Design in the Wild-One Board.