Unit 1c

Simulating the Shifter Sub-Block

Generate and Examine the VHDL

Now that you have completely described the behavior of our Shifter sub-block in a flowchart view, we should examine the VHDL which is produced. From the Design Browser, generate the VHDL for the Shifter sub-block.

Since this is a decent sized design, there is a good chance that you will encounter an error or two the first time that you try to generate. If you do encounter errors, go back to the flowchart view and try to locate and correct them.

Once you have generated the shifter VHDL without errors, go to the HDL frame of the Design Browser, expand the ALU library tree, and double-click on the entry titled shifter_flow.vhd to open the VHDL code in a notepad window.

Take a few minutes to examine the code. Notice that the architecture description for the Shifter does not contain any component declarations or instantiations. Instead, there is a process block labelled process0. This process block contains the sequence of statements which you entered in the Decision Boxes and Action Boxes of the flowchart. The declarative region of hte process block also contains the declarations of all of the variables that were used in the flowchart to store intermediate results.

Simulating the Shifter Sub-block

As with the Logical sub-block, just creating the design in FPGA Advantage is not enough, we must also verify that the design was entered correctly and that, if so, it works as intended. To do this, we will once again load the design into ModelSim, manually stimulate the input signals, and then examine the outputs in the Waves window.

First, you will need to compile the Shifter sub-block for simulation just as we did the Logical sub-block. Do this and then start the simulator from the Design Browser window running the compiled Shifter design data.

Now we need to test the design. The following table will list the test vectors which we will use and the expected results. You will need to create a ModelSim macro file, configure the Waves window, run the macro file, and verify the results.

A
ALUOp
ALUOp
ALUOp
SHAMT_HIGH
SHAMT
Result
 
(SLL)
(SRL)
(SRA)
SHAMT_HIGH
SHAMT
SLL
SRL
SRA
X"FEDCBA9876543210"
00
10
11
0
00000
X"FEDCBA9876543210"
X"FEDCBA9876543210"
X"FEDCBA9876543210"
X"FEDCBA9876543210"
00
10
11
0
00100
X"EDCBA98765432100"
X"0FEDCBA987654321"
X"FFEDCBA987654321"
X"FEDCBA9876543210"
00
10
11
0
01000
X"DCBA987654321000"
X"00FEDCBA98765432"
X"FFFEDCBA98765432"
X"FEDCBA9876543210"
00
10
11
0
01100
X"CBA9876543210000"
X"000FEDCBA9876543"
X"FFFFEDCBA9876543"
X"FEDCBA9876543210"
00
10
11
0
10000
X"BA98765432100000"
X"0000FEDCBA987654"
X"FFFFFEDCBA987654"
X"FEDCBA9876543210"
00
10
11
0
10100
X"A987654321000000"
X"00000FEDCBA98765"
X"FFFFFFEDCBA98765"
X"FEDCBA9876543210"
00
10
11
0
11000
X"9876543210000000"
X"000000FEDCBA9876"
X"FFFFFFFEDCBA9876"
X"FEDCBA9876543210"
00
10
11
0
11100
X"8765432100000000"
X"0000000FEDCBA987"
X"FFFFFFFFEDCBA987"
X"FEDCBA9876543210"
00
10
11
1
00000
X"7654321000000000"
X"00000000FEDCBA98"
X"FFFFFFFFFEDCBA98"

The above table lists a single test pattern for the input A which will be tested with several possible shifts. Although not a completely rigorous testing of the Shifter funcitonality, it should serve to expose almost any error in your design in the limited time we have for this tutorial.

One important case has been left out of the test, however, which you will also need to test. We have tested the right logical and arithmetic shifts with a vector that, if interpreted as two's complement, is a a negative number. We have not tested to make sure that the right shifts will work correctly with a positive number.

Change the test pattern for the input, A, so that the highest order bit is a '0' instead of a '1'. Run this pattern for several different shift amounts of both arithmetic and logical right shift and verify that the behavior is correct.

Now that you have finished testing the Shifter, we will move on to the next section of our design, Creating the Arithmetic sub-block