Design Specification for the Mentor Graphics Tutorial

Before we begin the tutorial, this page will provide a black box description of the device that you will design. What you see in the figure below, is an external description of the device called a  symbol in the Mentor tools. This is the basic method for implementing hierarchical designs and for supporting design abstraction. The symbol tells us the input and output specification, but we have no way of knowing what is going on inside. In fact, over the course of the design we may use several design descriptions interchangeably the same way that several architectural descriptions may be provided for a single entity descriptions in VHDL. In fact this is the graphical equivalent of the entity statement in VHDL.

For the purposes of this tutorial, the I/O architecture is fixed by the processor design from your text.  The signal type and direction of each signal is described in the following table.
 
INPUTS
A(63 downto 0) Operand A is a 64 bit input bus carrying the "A" operand for an ALU operation. 
B(63 downto 0) Operand B is a 64 bit input bus carrying the "B" operand for an ALU operation. 
ALUOp(3 downto 0) ALUOp is a 4 bit input bus which controls which operation the ALU executes. 
SHAMT(4 downto 0) SHAMT is a 5 bit input bus which forms the 5 least significant bits of a 6 bit shift amount. The 6 bit shift amount indicates the number of bits to shift the operand in a shift operation. 
SHAMT_HIGH SHAMT_HIGH is a single input bit that is combined with SHAMT(4 downto 0) to form a 6 bit shift amount. SHAMT_HIGH is the most significant bit of the 6 bit shift amount. 
OUTPUTS
R(63 downto 0) R is a 64 bit output bus which will hold the result of the ALU Operation. 
Zero Zero is a single bit output which will be set high if the result of an arithmetic operation is equal to zero and low otherwise. 
Overflow Overflow is a single bit output which will be set high if the execution of an arithmetic operation results in an overflow of the adder/subtractor and low otherwise. 

For reference as you implement the design, the functionality of the ALU is listed below. As above, these functions have been determined by the hardware operations of the MIPS R2000 instruction set and the role of the ALU in each operation. We will look into this process in detail when we design the control unit for our microprocessor. For now, we will assume that we have been handed a set of specfications that describe the set of functions that the ALU must implement. They will be encoded on to the ALUOp and the SHAMT_HIGH and SHAMT inputs. Although the ALUOp encodings would typically be fixed as well, I will leave this to you as an excercise (HINT: pay attention to the instruction set encodings). After all, you will eventually design the control unit as well.
 
Name of Operation Description of Operation
Add Signed (ADD)  R = A + B : Treating A, B, and R as signed two's complement integers. 
Add Unsigned (ADDU)  R = A + B : Treating A, B, and R as unsigned integers. 
Bitwise AND (AND)  R(i) = A(i) AND B(i). 
Bitwise NOR (NOR)  R(i) = A(i) NOR B(i). 
Bitwise OR (OR)  R(i) = A(i) OR B(i). 
Set on Less Than (SLT)  R = "000...01" if A < B otherwise R = "000....00" : Treating A and B as signed two's-complement integers. 
Set on Less Than Unsigned(SLTU)  R = "000....01" if A < B otherwise R = "000....00" : Treating A and B as unsigned integers. 
Shift Left Logical (SLL)  R = A << (SHAMT_HIGH concatenated with SHAMT) : filling in vacated bits with '0'. 
Shift Right Arithmetic (SRA)  R = A >> (SHAMT_HIGH concatenated with SHAMT) : filling in vacated bits with replicas of the sign bit, A(63). 
Shift Right Logical (SRL)  R = A >> (SHAMT_HIGH concatenated with SHAMT) : filling in vacated bits with '0'. 
Subtract Signed (SUB)  R = A - B : Treating A, B, and R as signed two's complement integers. 
Subtract Unsigned (SUBU)  R = A - B : Treating A, B, and R as unsigned integers. 
Bitwise XOR (XOR)  R(i) = A(i) XOR B(i). 

We are now ready to start up to tools and set up your design libraries.   Click here to continue