Design of the ALU Tester

The figure below depicts the architecture of your ALU tester module. It can be thought of as having two main sub-sections, one for the generation of test cases and the other to verify the result of the test case. The clock is the only input to the Test Case Generator which produces new inputs for the ALU (A, B, ALUop and SHAMT) on every the falling edge of every cycle. These generated inputs are also needed by each of the Verification Units so that the correct result can be calculated internally. On the next rising edge, the ALU’s result from the test case (R, Zero, and Overflow) is fed back into the tester and is compared to the expected value. The edges for test case generation and verification are off-setting so as to avoid having a race condition.

Figure 4.

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