assert_quiescent

Ensures that the value of a specified state expression equals a corresponding check value if a specified sample event has transitioned to TRUE.


	Parameters: severity_level width property_type msg coverage_level	Class: 2-cycle assertion

Syntax

Parameters


	severity_level	Severity of the failure. Default: ‘OVL_ERROR.
	width	Width of the state_expr and check_value arguments. Default: 1.
	property_type	Property type. Default: ‘OVL_ASSERT.
	msg	Error message printed when assertion fails. Default: “VIOLATION”.
	coverage_level	Coverage level. Default: ‘OVL_COVER_ALL.

Ports


clk		Clock event for the assertion. The checker samples on the rising edge of the clock.
reset_n		Active low synchronous reset signal indicating completed initialization.
state_expr	[ width - 1: 0 ]	Expression that should have the same value as check_value on the rising edge of clk if sample_event transitioned to TRUE in the previous clock cycle (or is currently transitioning to TRUE).
check_value	[ width - 1: 0 ]	Expression that indicates the value state_expr should have on the rising edge of clk if sample_event transitioned to TRUE in the previous clock cycle (or is currently transitioning to TRUE).
sample_event		Expression that initiates the quiescent state check when its value transitions to TRUE.

Description

The assert_quiescent_state assertion checker checks the expression sample_event at each rising edge of clk to see if its value has transitioned to TRUE (i.e., its current value is TRUE and its value on the previous rising edge of clk is not TRUE). If so, the checker verifies that the current value of state_expr equals the current value of check_value. The assertion fails if state_expr is not equal to check_value.

The state_expr and check_value expressions are verification events that can change. In particular, the same assertion checker can be coded to compare different check values (if they are checked in different cycles).

The checker is useful for verifying the states of state machines when transactions complete.

Assertion Check


	ASSERT_QUIESCENT_STATE	The sample_event expression transitioned to TRUE, but the values of state_expr and check_value were not the same.

Cover Points

Notes

1. The assertion check compares the current value of sample_event with its previous value. Therefore, checking does not start until the second rising clock edge of clk after reset_n deasserts.

2. The checker recognizes the Verilog macro ‘OVL_END_OF_SIMULATION=eos_signal. If set, the quiescent state check is also performed at the end of simulation, when eos_signal asserts (regardless of the value of sample_event).

3. Formal verification tools and hardware emulation/acceleration systems might ignore this checker.

assert_quiescent_state #(
	‘OVL_ERROR, 4, ‘OVL_ASSERT, “Error: illegal end of transaction”, ‘OVL_COVER_ALL)		// severity_level // width // property_type // msg // coverage_level
	valid_end_of_transaction_state (
		clk, reset_n, transaction_state, prev_tr == ‘TR_READ ? ‘TR_IDLE : ‘TR_WAIT end_of_transaction);	// clock // reset // state_expr // check_value // sample_event

assert_quiescent_state