assert_fifo

Ensures that a FIFO-type structure never overflows or underflows. This checker can be configured to support multiple pushes (FIFO writes) and pops (FIFO reads) during the same clock cycle.


	Parameters: severity_level depth push_width pop_width property_type msg coverage_level simultaneous_push_pop	Class: n-cycle assertion

Syntax

Parameters


	severity_level	Severity of the failure. Default: ‘OVL_ERROR.
	depth	Maximum number of elements in the FIFO or queue structure. This parameter must be > 0. Default: 1.
	push_width	Width of the push argument. Default: 1.
	pop_width	Width of the pop argument. Default: 1.
	property_type	Property type. Default: ‘OVL_ASSERT.
	msg	Error message printed when assertion fails. Default: “VIOLATION”.
	coverage_level	Coverage level. Default: ‘OVL_COVER_ALL.
	simultaneous_push_pop	Whether or not to allow simultaneous push/pop operations in the same clock cycle. When set to 0, if push and pop operations occur in the same cycle, the assertion fails. Default: 1 (simultaneous push/pop operations are allowed).

Ports


clk		Clock event for the assertion. The checker samples on the rising edge of the clock.
reset_n		Active low synchronous reset signal indicating completed initialization.
push	[push_width - 1: 0]	Expression that indicates the number of push operations that will occur during the current cycle.
pop	[pop_width - 1: 0]	Expression that indicates the number of pop operations that will occur during the current cycle.

Description

The assert_fifo_index assertion checker tracks the numbers of pushes (writes) and pops (reads) that occur for a FIFO or queue memory structure. This checker does permit simultaneous pushes/pops on the queue within the same clock cycle. It ensures the FIFO never overflows (i.e., too many pushes occur without enough pops) and never underflows (i.e., too many pops occur without enough pushes). This checker is more complex than the assert_no_overflow and assert_no_underflow checkers, which check only the boundary conditions (overflow and underflow respectively).

Assertion Checks


	OVERLOW	Push operation overflowed the FIFO.
	UNDERFLOW	Pop operation underflowed the FIFO.
	ILLEGAL PUSH AND POP	Push and pop operations performed in the same clock cycle, but the simultaneous_push_pop parameter is set to 0.

Cover Points


	fifo_push	Push operation.
	fifo_pop	Pop operation.
	fifo_full	FIFO full.
	fifo_empty	FIFO empty.
	fifo_simultaneous_push_pop	Push and pop operations in the same clock cycle.

Errors


	Depth parameter value must be > 0	Depth parameter is set to 0.

Notes

1. The checker checks the values of the push and pop expressions. By default, (i.e., simultaneous_push_pop is 1), “simultaneous” push/pop operations are allowed. In this case, the checker assumes the design properly handles simultaneous push/pop operations, so it only ensures that the FIFO buffer index at the end of the cycle has not overflowed or underflowed. The assertion cannot ensure the FIFO buffer index does not overflow between a push and pop performed in the same cycle. Similarly, the assertion cannot ensure the FIFO buffer index does not underflow between a pop and push performed in the same cycle.

See also

Examples


assert_fifo_index #(
	‘OVL_ERROR, 8, 1, 1, ‘OVL_ASSERT, “Error”, ‘OVL_COVER_ALL, 1)		// severity_level // depth // push_width // pop_width // property_type // msg // coverage_level // simultaneous_push_pop
	no_over_underflow (
		clk, reset_n, push, pop);	// clock // reset // push // pop

Ensures that an 8-element FIFO never overflows or underflows. Only single pushes and pops can occur in a clock cycle (push_width and pop_width values are 1). A push and pop operation in the same clock cycle is allowed (value of simultaneous_push_pop is 1).


assert_fifo_index #(
	‘OVL_ERROR, 8, 1, 1, ‘OVL_ASSERT, “violation”, ‘OVL_COVER_ALL 0)		// severity_level // depth // push_width // pop_width // property_type // msg // coverage_level // simultaneous_push_pop
	no_over_underflow (
		clk, reset_n, push, pop);	// clock // reset // push // pop

Ensures that an 8-element FIFO never overflows or underflows and that in no cycle do both push and pop operations occur.