Description

This course focuses on the techniques of quantitative analysis and evaluation of modern computing
systems. The emphasis is on the major component subsystems of high performance computers:
pipelining, instruction level parallelism, memory hierarchy, input/output, and network-oriented
interconnections. Students will undertake subsystem analysis projects.

Instructor, Fall 1998

Henry Chuang
      316 Alumni Hall, 624-8424, chuang@cs.pitt.edu
       Office Hours: M  1-3
                                T  2-4
Teaching Assistant:
      Longjiang Yang, 314 Alumni Hall, 624-8402, ylj@cs.pitt.edu
      Office Hours:

Text Book

J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 2nd Edition,
Morgan Kaufmann Publishing Co.

Grading

    Midterm exam: 25%
    Final exam     :  30 %
    Homeworks   :  20%
    Projects (2)    :  20%
    Class participation: 5%

Lecture Plan

Week 1

• Course introduction and overview
• Application and technology trends
• Performance, Benchmarks, and Metrics

• Performance rules of thumbs
• Amdahl's Law
• CPI formula

• Instruction set architecture
• The DLX architecture
• Introduction to pipelining
• Pipeline hazards and stalls

• Data hazards, forwarding
• Control hazards
• Delayed branch

• Dealing with exceptions and interrupts
• Multicycle operations
• Instruction level parallelism and advanced pipelining
• Dynamic scheduling
• Scoreboard

• Tomasulo Algorithm
• Dynamic branch prediction
• Superscalar, VLIW, Software pipelining
• Speculation

• Midterm exam
• Memory hierarchy, motivation, implementation
• Cache misses
• causes of misses & ways to reduce misses

• Midterm review
• Ways to reduce miss penalty
• Main memory organization
• Main memory performance enhancement

• DRAM-specific memory organization
• Cache data consistency and I/O
• Cache case study: the Alpha AXP 21064

• I/O, Storage devices
• Buses and interfaces
• A little Queuing theory

• RAID
• I/O system design

• Networks, architectural issues including topologies
• Networks, implementation and performance issues

• Internetworking
• Multiprocessing, multiprocessors

• Multiprocessor, cache coherency
• Snoopy caches and directory schemes
• Multiprocessors: case study

 Projects (Notes have been added to clarify questions concerning (1) write stalls at write buffer, and (2) write buffer hit)

 Assignments

 Slides-patterson

 Some  Slides

 Software Tools
 
  Additional Resources