cs2410 papers page

U of Pittsburgh CS2410 - Fall 2007
Paper List

For Homework #2
1. M. Tremblay, F. Chan, S. Chaudhry, A. W. Conigliaro, and S. S. Tse. The MAJC Architecture: A Synthesis of Parallelism and Scalability, IEEE Micro, 2000.
2. D. A. Patterson and D. R. Ditzel. The Case for the Reduced Instruction Set Computer, ACM SIGARCH Computer Architecture News, 1980.
3. Crusoe article #1. The Technology Behind Crusoe Processors, 2000.
4. Crusoe article #2. Transmeta Breaks x86 Low-Power Barrier, 2000.
5. Crusoe article #3. Transmeta Crusoe and efficeon: Embedded VLIW as a CISC Implementation, 2003.

Articles re: pipeline implementation
1. J. E. Smith and A. R. Pleszkun. Implementing Precise Interrupts in Pipelined Processors, IEEE Trans. Computers, May 1988.
2. W. S. Weiss and J. E. Smith. Instruction Issue Logic for Pipelined Supercomputers, Int'l Symp. Computer Architecture, June 1984.

For Homework #3
1. D. W. Wall. Limits of Instruction-Level Parallelism, Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 1991.
2. M. H. Lipasti, C. B. Wilkerson, and J. P. Shen. Value Locality and Load Value Prediction, Proc. Int'l Symp. Architectural Support for Programming Languages and Operating Systems, Oct. 1996.

For Homework #4
1. N. P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. Int'l Symp. Computer Architecture, May 1990.
2. Z. Zhang, Z. Zhu, and X. Zhang. A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality, Proc. Int'l Symp. Microarchitecture, Dec. 2000.

For Homework #5
1. M. Zhang and K. Asanovic. Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors, Proc. Int'l Symp. Computer Architecture, June 2005.
2. B. M. Beckmann, M. R. Marty, and D. A. Wood. ASR: Adaptive Selective Replication for CMP Caches, Proc. Int'l Symp. Microarchitecture, Dec. 2006.

For Homework #6
1. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically Characterizing Large Scale Program Behavior, Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems, 2002.
2. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling, Proc. Int'l Symp. Computer Architecture, 2003.

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