Project: RADAR (reliability-aware design and adaptive reconfiguration)

Various reliability issues have manifested; for example, increased process variation may cause unexpected circuit failures. Processor chip yields are staggering due to aggressive scaling and high complexity involved in the design and manufacturing process. In this research, we are investigating how processor design practices have to be changed to overcome the serious reliability and yield erosion problems. This project is supported partly by a grant from the NSF and A. Richard Newton Graduate Research Scholarship from DAC. This research is jointly done with Prof. Bruce Childers.

Selected Publications

• Musfiq Rahman, Bruce R. Childers and Sangyeun Cho, COMeT: Continuous Online Memory Test, Proceedings of the 17th IEEE Pacific Rim Int'l Symposium on Dependable Computing (PRDC), pp. 109~118, Pasadena, California, December 2011. (pdf) (pptx)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, DEFCAM: A Design and Evaluation Framework for Defect-Tolerant Cache Memories, ACM Transactions on Architecture and Code Optimization (TACO), 8(3):17:1~17:29, October 2011. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, CloudCache: Expanding and Shrinking Private Caches Proceedings of the IEEE Int'l Symposium on High-Performance Computer Architecture (HPCA), San Antonio, TX, February 2011. (pdf) (pptx)

• Musfiq Rahman, Sangyeun Cho, and Bruce R. Childers, StealthWorks: Emulating Main Memory Errors, Proceedings of the 1st International Conference on Runtime Verification (RV 2010), pp. 360~367, Sliema, Malta, November 2010. A short paper. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, PERFECTORY: A Fault-Tolerant Directory Memory Architecture, IEEE Transactions on Computers (TC), 59(5):638~650, May 2010. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, StimulusCache: Boosting Performance of Chip Multiprocessors with Excess Cache, Proceedings of the IEEE Int'l Symposium on High-Performance Computer Architecture (HPCA), pp. 211~222, Bangalore, India, January 2010. (pdf) (pptx)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, Exploring the Interplay of Yield, Area, and Performance in Processor Caches, Proceedings of the IEEE Int'l Conference on Computer Design (ICCD), pp. 216~223, Lake Tahoe, CA, October 2007. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, Performance of Graceful Degradation for Cache Faults, Proceedings of the IEEE Computer Society Symposium on VLSI (ISVLSI), pp. 409~415, Porto Alegre, Brazil, May 2007. (pdf)

• Sangyeun Cho, I-Cache Multi-Banking and Vertical Interleaving, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 14~19, Stresa-Lago Maggiore, Italy, March 2007. (pdf)