Publications

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2010

• Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, and Sangyeun Cho, Two-Phase Trace-driven Simulation (TPTS): A fast multicore processor architecture simulation approach, Software: Practice and Experience (SPE), 2010, to appear.

• Sangyeun Cho and Rami Melhem, On the Interplay of Parallelization, Program Performance and Energy Consumption, IEEE Transactions on Parallel and Distributed Systems (TPDS), 2010, to appear.

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, PERFECTORY: A Fault-Tolerant Directory Memory Architecture, IEEE Transactions on Computers (TC), 2010, to appear.

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, StimulusCache: Boosting Performance of Chip Multiprocessors with Excess Cache, Proceedings of the IEEE Int'l Symposium on High-Performance Computer Architecture (HPCA), Bangalore, India, January 2010.

2009

• Sangyeun Cho and Hyunjin Lee, Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance, Proceedings of the IEEE/ACM Int'l Symposium on Microarchitecture (MICRO), New York City, New York, December 2009.

• Michel Hanna, Socrates Demetriades, Sangyeun Cho, and Rami Melhem, Progressive Hashing for Packet Processing Using Set-Associative Memory, Proceedings of the ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Princeton, New Jersey, October 2009. (pdf)

• Sangyeun Cho and Lory Al Moakar, Augmented FIFO Cache Replacement Policies for Low-Power Embedded Processors, Journal of Circuits, Systems, and Computers (JCSC), Vol. 18, No. 6, pp. 1081~1092, October 2009. (pdf)

• Lei Jin and Sangyeun Cho, SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors, Proceedings of the Int'l Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 361~371, Raleigh, North Carolina, September 2009. (pdf) (pptx)

• Mohammad H. Hammoud, Sangyeun Cho, and Rami Melhem, Dynamic Cache Clustering for Chip Multiprocessors, Proceedings of the ACM Int'l Conference on Supercomputing (ICS), IBM T. J. Watson Research Center, New York, June 2009. (pdf) (ppt)

• Taecheol Oh, Hyunjin Lee, Kiyeon Lee, and Sangyeun Cho, An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor, Proceedings of the IEEE Computer Society Symposium on VLSI (ISVLSI), Tampa, Florida, May 2009. (pdf) (pptx)

• Michel Hanna, Socrates Demetriades, Sangyeun Cho, and Rami Melhem, CHAP: Enabling Efficient Hardware-based Multiple Hash Schemes for IP Lookup, Proceedings of the IFIP Int'l Conference on Networking (Networking), pp. 756~769, Aachen, Germany, May 2009. (pdf) (pptx)

• Kiyeon Lee, Shayne Evans, and Sangyeun Cho, Accurately Approximating Superscalar Processor Performance from Traces, Proceedings of the IEEE Int'l Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 238~248, Boston, Massachusetts, April 2009. (pdf) (pptx)

• Mohammad H. Hammoud, Sangyeun Cho, and Rami Melhem, ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors, Proceedings of the 4th Int'l Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), pp. 355~372, Paphos, Cyprus, January 2009. (pdf) (ppt)

2008

• Sangyeun Cho, Michael Moeng, and Rami Melhem, Energy Corollaries to Amdahl's Law, Microprocessor Report (MPR), 10/6/2008 issue, October 2008. (pdf)

• Choongyeun Cho, Daeik Kim, Jonghae Kim, Daihyun Lim, and Sangyeun Cho, Early Prediction of Product Performance and Yield via Technology Benchmark, Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 205~208, San Francisco, California, September 2008. (pdf) (slides)

• Lei Jin and Sangyeun Cho, Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches, Proceedings of the Int'l Conference on Parallel Processing (ICPP), pp. 487~494, Portland, Oregon, September 2008. (pdf)

• Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, and Michael Moeng, TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation, Proceedings of the Int'l Conference on Parallel Processing (ICPP), pp. 446~453, Portland, Oregon, September 2008. (pdf) (pptx)

• Socrates Demetriades, Michel Hanna, Sangyeun Cho, and Rami Melhem, An Efficient Hardware-based Multi-hash Scheme for High Speed IP Lookup, Proceedings of the Annual IEEE Symposium on High-Performance Interconnects (HOTI), Stanford, California, August 2008. (pdf)

• Sangyeun Cho, Tao Li, and Onur Mutlu, Interaction of Many-core Computer Architecture and Operating Systems, IEEE Micro, 28(3):2~5, May/June 2008. Guest Editors' Introduction Article. (pdf)

• Jongbae Kim, Sangyeun Cho, and Seung-Jae Kim, Preliminary Studies to Develop a Ubiquitous Computing and Health-monitoring System for Wheelchair Users, Proceedings of the ACM Int'l Conference on Body Area Networks (BodyNets), work-in-progress paper, Tempe, AZ, March 2008. (pdf)

• Choongyeun Cho, Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, and Robert Trzcinski, Decomposition and Analysis of Process Variability Using Constrained Principal Component Analysis, IEEE Transactions on Semiconductor Manufacturing (TSM), 21(1):55~62, February 2008. (pdf)

• Sangyeun Cho and Rami Melhem, Corollaries to Amdahl's Law for Energy, IEEE Computer Architecture Letters (CAL), 7(1):25~28, January 2008 (published on-line in December 2007). (pdf)

2007

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, Exploring the Interplay of Yield, Area, and Performance in Processor Caches, Proceedings of the IEEE Int'l Conference on Computer Design (ICCD), pp. 216~223, Lake Tahoe, CA, October 2007. (pdf)

• Sangyeun Cho, Lei Jin, and Kiyeon Lee, Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems, Proceedings of the IEEE Int'l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 3~11, Daegu, Korea, August 2007. Invited paper. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, Performance of Graceful Degradation for Cache Faults, Proceedings of the IEEE Computer Society Symposium on VLSI (ISVLSI), pp. 409~415, Porto Alegre, Brazil, May 2007. (pdf)

• Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, and Rami Melhem, CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications, Proceedings of the IEEE Int'l Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 230~241, San Jose, California, April 2007. (pdf) (ppt)

• Choongyeun Cho, Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, and Robert Trzcinski, A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology, Proceedings of the Int'l Symposium on Quality Electronic Design (ISQED), pp. 699~702, San Jose, California, March 2007. (pdf) (ppt)

• Sangyeun Cho, I-Cache Multi-Banking and Vertical Interleaving, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 14~19, Stresa-Lago Maggiore, Italy, March 2007. (pdf)

• Lei Jin and Sangyeun Cho, Better than the Two: Exceeding Private and Shared Caches via Two-Dimensional Page Coloring, Proceedings of the Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), during the IEEE Int'l Symposium on High-Performance Computer Architectures (HPCA), Phoenix, Arizona, February 2007. (pdf)

• Sangyeun Cho and Rami Melhem, A Scalable and Reconfigurable Search Memory Substrate for High Throughput Packet Processing, Presented at the IEEE 21st Annual Computer Communications Workshop (CCW), Pittsburgh, Pennsylvania, February 2007. Invited presentation. (ppt)

2006

• Sangyeun Cho and Lei Jin, Managing Distributed, Shared L2 Caches through OS-Level Page Allocation, Proceedings of the IEEE/ACM Int'l Symposium on Microarchitecture (MICRO), pp. 455~465, Orlando, Florida, December 2006. Nominated for the best paper award. (pdf) (ppt)

• Lei Jin, Hyunjin Lee, and Sangyeun Cho, A Flexible Data to L2 Cache Mapping Approach for Future Multicore Processors, Proceedings of the ACM Workshop on Memory Systems Performance and Correctness (MSPC) during the ACM Int'l Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 92~101, San Jose, California, October 2006. (pdf)

• Lei Jin and Sangyeun Cho, Reducing Cache Traffic and Energy with Macro Data Load, Proceedings of the ACM Int'l Symposium on Low Power Electronics and Design (ISLPED), pp. 147~150, Tegernsee, Germany, October 2006. (pdf) (ppt)

• Lei Jin and Sangyeun Cho, A Characterization Study on Memory Value Reuse, Proceedings of the Workshop on Memory Performance Issues (WMPI) during the IEEE Int'l Symposium on High-Performance Computer Architectures (HPCA), Austin, Texas, February 2006. (pdf)

Before 2004 (or Before Pitt)

• Sangyeun Cho, Seung-Jae Chung, Sang-Hyun Park, Sangwoo Kim, Sungjin Jung, Wooyoung Jung, Sanghoon Moon, and Yong-Chun Kim, CPAD4: A Highly Integrated Low Power Digital Audio Chip, Proceedings of the IEEE Int'l Symposium on Low-Power and High-Speed Chips (Cool Chips), Tokyo, Japan, April 2002.

• Sangyeun Cho, Wooyoung Jung, Yongchun Kim, and Seh-Woong Jeong, A Low-Power Cache Design for CalmRISC^TM-Based Systems, Proceedings of the Int'l Conference on Computer Design (ICCD), pp. 394~399, Austin, Texas, September 2001. (pdf)

• Sangyeun Cho, Pen-Chung Yew, and Gyungho Lee, A High-Bandwidth Memory Pipeline for Wide Issue Processors, IEEE Transactions on Computers, Vol. 50, No. 7, pp. 709~723, July 2001. (pdf)

• Sangyeun Cho, Sanghyun Park, Sangwoo Kim, Yongchun Kim, Seh-Woong Jeong, Bong-Young Chung, Hyung-Lae Roh, Chang-Ho Lee, Hoon-Mo Yang, Seung-Ho Kwak, and Moon-Key Lee, CalmRISC^TM-32: A 32-Bit Low Power MCU Core, Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs (AP-ASIC), pp. 285~289, Cheju, Korea, August 2000. (pdf)

• Chang-Ho Lee, Hoon-Mo Yang, Seung-Ho Kwak, Moon-Key Lee, Sanghyun Park, Sangyeun Cho, Sangwoo Kim, Yongchun Kim, Seh-Woong Jeong, Bong-Young Chung, and Hyung-Lae Roh, Efficient Random Vector Verification Method for an Embedded 32-Bit MCU Core, Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs (AP-ASIC), pp. 291~294, Cheju, Korea, August 2000. (pdf)

• Sangyeun Cho, Pen-Chung Yew, and Gyungho Lee, Access Region Locality for High-Bandwidth Processor Memory System Design, Proceedings of the IEEE/ACM Int'l Symposium on Microarchitecture (MICRO), pp. 136~146, Haifa, Israel, November 1999. (pdf) (ppt)

• Sangyeun Cho, Pen-Chung Yew, and Gyungho Lee, Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor, Proceedings of the ACM Int'l Symposium on Computer Architecture (ISCA), pp. 100~110, Atlanta, Georgia, May 1999. (pdf)

• Sangyeun Cho, Jinseok Kong, and Gyungho Lee, Coherence and Replacement Protocol of DICE - A Bus-Based COMA Multiprocessor, Journal of Parallel and Distributed Computing (JPDC), Vol. 57, No. 1, pp. 14~32, April 1999. (pdf)

• Gyungho Lee, Bland W. Quattlebaum, Sangyeun Cho, and Larry L. Kinney, Design of a Bus-Based Shared-Memory Multiprocessor DICE, Microprocessors and Microsystems, Vol. 22, No. 7, pp. 403~411, March 1999. (pdf)

• Sangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia Zheng, Steve J. Schwinn, Xin Wang, Qing Zhao, Zhiyuan Li, David Lilja, and Pen-Chung Yew, High-Level Information - An Approach for Integrating Front-End and Back-End Compilers, Proceedings of the Int'l Conference on Parallel Processing (ICPP), pp. 346~355, Minneapolis, Minnesota, August 1998. (pdf)

• Sangyeun Cho, Jinseok Kong, and Gyungho Lee, On Timing Constraints of Snooping in a Bus-Based COMA Multiprocessor, Microprocessors and Microsystems, Vol. 21, No. 5, pp. 313~318, February 1998. (pdf)

• Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, and Larry Kinney, Global Bus Design of a Bus-Based COMA Multiprocessor DICE, Proceedings of the IEEE Int'l Conference on Computer Design (ICCD), pp. 231~240, Austin, Texas, October 1996. (pdf)

• Sangyeun Cho and Gyungho Lee, Reducing Coherence Overhead in Shared-Bus Multiprocessors, Proceedings of Euro-Par, pp. 492~497, Lyon, France, August 1996. (pdf)