Project: MMC (malleable many-core architectures)

Multicore processors (having multiple processor "cores" on a single chip) are ubiquitous and we will find chips having many more cores in the future. The key question for the next-generation multicore processor is: How can we utilize the increased amount of on-chip resources (cores, caches and interconnects) efficiently to achieve scalable performance, low power, high availability and dependability? We aim to explore novel multicore processor architectures and systems to answer the question. Moreover, we have been developing efficient trace-driven simulation, analytical modeling and technology modeling strategies for multicore research. This project is supported partly by grants (CCF-1059283 and CCF-1059202) from the NSF.

Selected Publications

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, DEFCAM: A Design and Evaluation Framework for Defect-Tolerant Cache Memories, ACM Transactions on Architecture and Code Optimization (TACO), 8(3):17:1~17:29, October 2011. (pdf)

• Michael Moeng, Sangyeun Cho, and Rami Melhem, Scalable Multi-Cache Simulation Using GPUs Proceedings of the IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Singapore, July 2011.

• Taecheol Oh, Kiyeon Lee, and Sangyeun Cho, An Analytical Performance Model for Co-Management of Last-Level Cache and Bandwidth Sharing, Proceedings of the IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Singapore, July 2011.

• Kiyeon Lee and Sangyeun Cho, In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces, Proceedings of the IEEE Int'l Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Singapore, July 2011.

• Sangyeun Cho and Socrates Demetriades, MAESTRO: Orchestrating Predictive Resource Management in Future Multicore Systems, Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), San Diego, CA, June 2011.

• Mohammad Hammoud, Sangyeun Cho, and Rami Melhem, C-AMTE: A Location Mechanism for Flexible Cache Management in Chip Multiprocessors, Journal of Parallel and Distributed Computing (JPDC), 71(6):889~896, June 2011. (pdf)

• Socrates Demetriades and Sangyeun Cho, BarrierWatch: Characterizing Multithreaded Workloads across and within Program-Defined Epochs, Proceedings of the ACM International Conference on Computing Frontiers (CF), Ischia, Italy, May 2011. (pdf) (pptx)

• Lei Jin and Sangyeun Cho, Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse, IEEE Transactions on Computers (TC), 60(4):526~537, April 2011. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, CloudCache: Expanding and Shrinking Private Caches Proceedings of the IEEE Int'l Symposium on High-Performance Computer Architecture (HPCA), San Antonio, TX, February 2011. (pdf) (pptx)

• Mohammad H. Hammoud, Sangyeun Cho, and Rami Melhem, Cache Equalizer: A Placement Mechanism for Chip Multiprocessor Distributed Shared Caches, Proceedings of the 6th Int'l Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Heraklion, Crete, Greece, January 2011. (pdf) (ppt)

• Mohammad H. Hammoud, Sangyeun Cho, and Rami Melhem, An Intra-Tile Cache Set Balancing Scheme, Proceedings of the Int'l Conference on Parallel Architectures and Compilation Techniques (PACT), Vienna, Austria, September 2010. A poster paper.

• Mohammad H. Hammoud, Sangyeun Cho, and Rami Melhem, A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors, IEEE Computer Architecture Letters (CAL), 9(1):29~32, January-June 2010. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, PERFECTORY: A Fault-Tolerant Directory Memory Architecture, IEEE Transactions on Computers (TC), 59(5):638~650, May 2010. (pdf)

• Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, and Sangyeun Cho, Two-Phase Trace-driven Simulation (TPTS): A fast multicore processor architecture simulation approach, Software: Practice and Experience (SPE), 40(3):239~258, March 2010. (pdf)

• Sangyeun Cho and Rami Melhem, On the Interplay of Parallelization, Program Performance and Energy Consumption, IEEE Transactions on Parallel and Distributed Systems (TPDS), 21(3):342~353, March 2010. (pdf)

• Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers, StimulusCache: Boosting Performance of Chip Multiprocessors with Excess Cache, Proceedings of the IEEE Int'l Symposium on High-Performance Computer Architecture (HPCA), pp. 211~222, Bangalore, India, January 2010. (pdf) (pptx)

• Lei Jin and Sangyeun Cho, SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors, Proceedings of the Int'l Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 361~371, Raleigh, North Carolina, September 2009. (pdf) (pptx)

• Mohammad H. Hammoud, Sangyeun Cho, and Rami Melhem, Dynamic Cache Clustering for Chip Multiprocessors, Proceedings of the ACM Int'l Conference on Supercomputing (ICS), pp. 56~67, IBM T. J. Watson Research Center, New York, June 2009. (pdf) (ppt)

• Taecheol Oh, Hyunjin Lee, Kiyeon Lee, and Sangyeun Cho, An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor, Proceedings of the IEEE Computer Society Symposium on VLSI (ISVLSI), pp. 181~186, Tampa, Florida, May 2009. (pdf) (pptx)

• Kiyeon Lee, Shayne Evans, and Sangyeun Cho, Accurately Approximating Superscalar Processor Performance from Traces, Proceedings of the IEEE Int'l Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 238~248, Boston, Massachusetts, April 2009. (pdf) (pptx)

• Mohammad H. Hammoud, Sangyeun Cho, and Rami Melhem, ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors, Proceedings of the 4th Int'l Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), pp. 355~372, Paphos, Cyprus, January 2009. (pdf) (ppt)

• Sangyeun Cho, Michael Moeng, and Rami Melhem, Energy Corollaries to Amdahl's Law, Microprocessor Report (MPR), 10/6/2008 issue, October 2008. (pdf)

• Choongyeun Cho, Daeik Kim, Jonghae Kim, Daihyun Lim, and Sangyeun Cho, Early Prediction of Product Performance and Yield via Technology Benchmark, Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 205~208, San Francisco, California, September 2008. (pdf) (slides)

• Lei Jin and Sangyeun Cho, Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches, Proceedings of the Int'l Conference on Parallel Processing (ICPP), pp. 487~494, Portland, Oregon, September 2008. (pdf)

• Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, and Michael Moeng, TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation, Proceedings of the Int'l Conference on Parallel Processing (ICPP), pp. 446~453, Portland, Oregon, September 2008. (pdf) (pptx)

• Sangyeun Cho, Tao Li, and Onur Mutlu, Interaction of Many-core Computer Architecture and Operating Systems, IEEE Micro, 28(3):2~5, May/June 2008. Guest Editors' Introduction Article. (pdf)

• Choongyeun Cho, Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, and Robert Trzcinski, Decomposition and Analysis of Process Variability Using Constrained Principal Component Analysis, IEEE Transactions on Semiconductor Manufacturing (TSM), 21(1):55~62, February 2008. (pdf)

• Sangyeun Cho and Rami Melhem, Corollaries to Amdahl's Law for Energy, IEEE Computer Architecture Letters (CAL), 7(1):25~28, January 2008 (published on-line in December 2007). (pdf)

• Sangyeun Cho, Lei Jin, and Kiyeon Lee, Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems, Proceedings of the IEEE Int'l Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 3~11, Daegu, Korea, August 2007. Invited paper. (pdf)

• Choongyeun Cho, Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, and Robert Trzcinski, A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology, Proceedings of the Int'l Symposium on Quality Electronic Design (ISQED), pp. 699~702, San Jose, California, March 2007. (pdf) (ppt)

• Sangyeun Cho, I-Cache Multi-Banking and Vertical Interleaving, Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 14~19, Stresa-Lago Maggiore, Italy, March 2007. (pdf)

• Lei Jin and Sangyeun Cho, Better than the Two: Exceeding Private and Shared Caches via Two-Dimensional Page Coloring, Proceedings of the Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), during the IEEE Int'l Symposium on High-Performance Computer Architectures (HPCA), Phoenix, Arizona, February 2007. (pdf)

• Sangyeun Cho and Lei Jin, Managing Distributed, Shared L2 Caches through OS-Level Page Allocation, Proceedings of the IEEE/ACM Int'l Symposium on Microarchitecture (MICRO), pp. 455~465, Orlando, Florida, December 2006. Nominated for the best paper award. (pdf) (ppt)

• Lei Jin, Hyunjin Lee, and Sangyeun Cho, A Flexible Data to L2 Cache Mapping Approach for Future Multicore Processors, Proceedings of the ACM Workshop on Memory Systems Performance and Correctness (MSPC) during the ACM Int'l Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp. 92~101, San Jose, California, October 2006. (pdf)

• Lei Jin and Sangyeun Cho, Reducing Cache Traffic and Energy with Macro Data Load, Proceedings of the ACM Int'l Symposium on Low Power Electronics and Design (ISLPED), pp. 147~150, Tegernsee, Germany, October 2006. A poster paper. (pdf) (ppt)

• Lei Jin and Sangyeun Cho, A Characterization Study on Memory Value Reuse, Proceedings of the Workshop on Memory Performance Issues (WMPI) during the IEEE Int'l Symposium on High-Performance Computer Architectures (HPCA), Austin, Texas, February 2006. (pdf)