Custom Counterflow Pipelines for Embedded Processors
Past Work - This Project is Completed.

In recent years, the design of custom embedded processors has gained tremendous attention due to the advantages of tailoring capabilities to embedded applications to improve performance, energy/power consumption, and resource utilization. An application-specific processor (ASP) has the flexibility to include the minimal instruction set and microarchitecture elements that give good performance and low cost without the complexity needed for general-purpose codes. Because cost and time-to-market constraints are important to embedded systems, an ASP architecture should permit automatic design, including high-level architectural design.

This research project studies how to build Counterflow Pipelines tailored to the resource and data flow requirements of embedded software. The Counterflow Pipeline is a novel pipeline organization proposed by Sproull, Sutherland, and Molnar. Although the CFP was originally proposed as a general-purpose organization, CFPs have several characteristics that make them very attractive for ASPs, including: local control, a simple and mostly regular structure, highly composable components, and inherent handling of a type of register renaming, speculative execution, and out-of-order execution.

This project has developed techniques that automatically customize a counterflow pipeline to an application expressed algorithmically in a high-level language. As part of this project, a novel architecture for building custom instruction-level parallel processors, called the Wide Counterflow Pipeline (WCFP), was developed. This architecture significantly improves upon the original CFP to make it better suited for obtaining high-performance for custom embedded processors.

Publications