#########################################
#		Inputs to the simulation		#
#########################################
import argparse
parser = argparse.ArgumentParser(description='Configuration options for this simulation.')

parser.add_argument('--program',
                    dest="program",
                    required=True,
                    action='store',
                    help='The program to run in the simulator')

parser.add_argument('--latencies',
                    dest="latencies",
                    required=True,
                    action='store',
                    help='The json file with the instruction latencies')
# Parse arguments
args = parser.parse_args()


## Print info ##
print("Running simulator using program "+args.program)
print("Latencies in  "+args.latencies)



#####################################
#	Load JSON file with latencies	#
#####################################
import json
with open(args.latencies, 'r') as inp_file:
  latencies=json.load(inp_file)
print("Latencies:")
print(json.dumps(latencies, indent=2))
# Latencies will look like
# {
#   "liz": 20,
#   "sw": 150,
#   "lw": 150,
#   "put": 1000,
#   "halt": 1,
# }

import sst
core = sst.Component("XSim","XSim.core")
core.addParams({
  "clock_frequency": "1GHz",
  "program": args.program,
  "verbose": 0
})
core.addParams(latencies)

# Get memory latency
memory = sst.Component("data_memory", "memHierarchy.MemController")
memory.addParams(
{
  'clock':                "1GHz",
  'backend':              "memHierarchy.simpleMem",
  'backend.mem_size':     "64KiB",
  'backend.access_time':  "100ns"
})


cpu_data_memory_link = sst.Link("cpu_data_memory_link")
cpu_data_memory_link.connect(
  (core,    "data_memory_link", "100ps"),
  (memory,  "direct_link",      "100ps")
)