Research scientist of Microarchitecture Research Lab, Intel Labs
Email: hyunjin.a.lee (at) intel.com
Curriculum Vitae
Research
I am currently a research scientist at the Microarchitecture Research
Lab in Intel Labs, Santa Clara, CA. Before joining Intel Labs, I completed my Ph.D.
in Computer Science from the University of Pittsburgh. I received B.S. in
Electrical Engineering from Seoul National University.
Ph.D. advisors: Prof.
Sangyeun Cho and Prof. Bruce R. Childers
Publication
TACO DEFCAM: A Design
and Evaluation Framework for Defect-Tolerant Cache Memories
Hyunjin Lee, Sangyeun Cho and Bruce R. Childers
ACM Transactions on Architecture and Code Optimization
(TACO), 8(3): Article 17, October 2011
HPCA CloudCache:
Expanding and Shrinking Private Caches
Hyunjin Lee, Sangyeun Cho and Bruce R. Childers
IEEE International Symposium on High-Performance Computer
Architecture (HPCA)
San Antonio, Texas, February 2011.
TC
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers
IEEE Transactions on Computer
(TC), 59(5):638~650, May 2010
SPE
Two-Phase Trace-driven Simulation (TPTS): A fast multicore
processor architecture simulation approach
Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades,
Michael Moeng, and Sangyeun
Cho
Software: Practice and
Experience (SPE), 40(3):239~258, March 2010
HPCA StimulusCache: Boosting Performance of Chip Multiprocessors
with Excess Cache
Hyunjin Lee, Sangyeun Cho and Bruce R. Childers
IEEE International Symposium on High-Performance Computer
Architecture (HPCA)
Bangalore, India, January 2010.
MICRO Flip-N-Write:
A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance
Sangyeun Cho and Hyunjin Lee
IEEE/ACM International Conference on Microarchitecture
(MICRO)
New York City, New York, December 2009.
ISVLSI An Analytical Model to Study Optimal Area Breakdown between
Cores and Caches in a Chip Multiprocessor
Taecheol Oh, Hyunjin Lee, Kiyeon Lee, and Sangyeun Cho
IEEE
Computer Society Annual Symposium on VLSI (ISVLSI)
Tampa, Florida, May 2009.
ICPP TPTS:
A Novel Framework for Very Fast Manycore Processor
Architecture Simulation
Sangyeun Cho, Socrates F. Demetriades, Shayne V. Evans, Lei Jin, Hyunjin
Lee, Kiyeon Lee,
and Michael Moeng
IEEE
International Conference on Parallel Processing (ICPP)
Portland, Oregon, September 2008.
ICCD
Exploring
the Interplay of Yield, Area, and Performance in Processor Caches
Hyunjin Lee, Sangyeun Cho,
and Bruce R. Childers
IEEE
International Conference on Computer Design (ICCD)
Lake Tahoe, CA, October 2007.
ISVLSI Performance
of Graceful Degradation for Cache Faults
Hyunjin Lee, Sangyeun Cho, and Bruce R. Childers
IEEE
Computer Society Annual Symposium on VLSI (ISVLSI)
Porto Alegre, Brazil, May 2007
MSPC A
Flexible Data to L2 Cache Mapping Approach for Future Multicore Processors
Lei Jin, Hyunjin Lee, and
Sangyeun Cho
ACM
Workshop Memory Systems Performance and Correctness (MSPC)
San Jose, California, October 2006
Teaching
CS/COE0449
Introduction to Systems Software,
(Instructor)
Summer 2010
CS/COE0447
Computer Organization and Assembly Language,
(Recitation TA) Spring/Fall
2006
Education
University of
Pittsburgh, Ph.D. in Computer
Science, August 2011
Seoul National
University, B.S. in Electrical
Engineering, February 1999
Industry Experience
Microsoft
Research Redmond, Washington
Worked on Efficient Distributed Tuple Space project
Samsung
Electronics, Co. Ltd. Kyeong-ki, Korea
Worked on DVD-Recorder SOC Projects in Semiconductor Division
Awards
A.
Richard Newton Graduate Scholarship
The 45th
Design Automation Conference (DAC) 2008
3rd Place, Hyunjin Lee, "An Extended Motion Estimation Algorithm Based on Discrete
Cosine Transform"
5th
HumanTech Thesis Prize, Samsung Electronics, Feb. 1999
Best Award (2nd place), Hyunjin
Lee "Enhanced MPEG-2 Motions Estimation Technique"
National
Thesis Competition for University Student, Ministry of Education, Korea, Dec. 1998