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Research Spotlight: Optoelectronic Computing Research Group Installs Clean Room for Chip Testing

The newest addition to the research facilities in Sennot Square is a 300 square foot, class 1000 clean room facility in the fifth floor optical computing lab. Dr. Chiarulli and Dr. Levitan use this facility in their research on high-speed optical and electronic data links for chip-to-chip and network-on-chip applications.

The clean room houses two high resolution chip-probing workstations that are capable of positioning contacts at test points on a opto-electronic integrated circuit chip surface with precision down to a few microns. Working at this resolution requires vibration stabilization, (yes Sennott Square shakes a bit!). Two isolation tables that literally float on compressed air provide stabilization. High-resolution optical microscopes provide direct-view stereo imaging as well as video imaging of the chip surface.  “The probe stations are our own home-brew design,” said Dr. Chiarulli. “Commercial probe stations cannot handle the optical setups that we need for our links. This system allows us to probe the test the chips while sending and receiving data in an active link.”

The lab will be testing three chips this summer and fall with experiments designed to test a new bus design that can reduce the area and power requirements of chip-to-chip interconnect on a PC board by as much as 45%. The first of these chips uses an optical interconnect based on a unique chip technology called “Silicon on Sapphire” in which the CMOS circuitry is fabricated on an optically transparent substrate. This allows optical I/O links to move through the bottom surface of the chip directly into an optical circuit board.

The other two chips will test electrical links with a similar architecture. The goal of these chips is to demonstrate a 40GB/s serialized bus using only six I/O pins on a device fabricated in .18um standard silicon CMOS.

The Defense Advanced Projects Agency, the National Science Foundation, the Optoelectronics Industry Device Association, and the Pittsburgh Technology Collaborative support projects in the optoelectronic-computing group. Sponsor companies within the Technology Collaborative for the chip-level interconnect project include OKI semiconductor, CISCO, and IBM. Peregrine Semiconductor and LSI Logic  have also contributed chip fabrication services.

 

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