Architecture Prelim (CS2410)

Format

The 2410 final exam will form the basis for the Ph.D. preliminary exam in computer architecture. There will be three sets of questions: Part I (first hour of exam period): 2410 final exam questions Part II (second hour of exam period): 2410/preliminary exam questions Part III (third hour of exam period): Preliminary exam questions Parts I and II form the 2410 final exam. Parts II and III form the preliminary exam in computer architecture. Part I does not count toward the preliminary exam and part III does not count toward the 2410 final exam. If you are taking only the 2410 final exam, then you have to do parts I and II. If you are taking only the preliminary exam, then you have to do parts II and III. If you are taking both the 2410 final and the preliminary exam, then you have to do parts I, II, and III. You will have an hour to do each part. Each part of the exam will be passed out at the beginning of the hour and collected at the end of the hour. Hence, if you finish one part early, you can not start on the next part. You have to wait until each part is passed out to begin it. If you are taking only the 2410 final exam, then you may leave once part II is completed or at the end of the second hour. If you are taking only the preliminary exam then you should arrive for the exam at the start of part II (the second hour of the exam period). Parts I and II will be graded by the course instructor. Part III will be graded by other members of the computer architecture preliminary exam faculty committee. Parts I, II and III will be anonymous (i.e., do not indicate your name on the exam booklet). The CS2410 final and preliminary exam date and time will be posted on the course website maintained by the current CS2410 instructor.

Reading List

Book
[1] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd Ed., Morgan Kaufmann, 2002.

The whole contents of the above book will be considered when problems are developed. Students must at least read the following chapters to fully acquaint themselves with the book content:

Chapter 1
Chapter 2
Chapter 3.1~3.8
Chapter 4.1~4.3
Chapter 5
Chapter 6.1~6.10
Chapter 7.1~7.10
Chapter 8.1~8.12
Appendix A

Papers
[1] N. P. Jouppi. “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers,” Proc. Int'l Symp. Computer Architecture, May 1990.
[2] S. McFarling. “Combining Branch Predictors,” WRL Technical Note TN-36, June 1993. Available at http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-36.pdf.
[3] D. Tullsen, S. J. Eggers, and H. M. Levy. “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proc. Int'l Symp. Computer Architecture, May 1995.

Refer to the prelim. exam. information at the departmental web page for other details. Topics of emphasis remain the same.

Topics of Emphasis

CPU Organization

• Instruction set architecture
• Processor implementation
• Performance metrics
• Pipelined and superscalar designs
• Dynamic branch prediction
• VLIW and EPIC organizations
• Digital signal processors and embedded processors

Memory Organization

• Physical memory system design
• Caching systems
• Virtual memory

Input/Output

• Bus organization
• Device architectures
• Disk arrays
• Multiple bus systems

Parallel systems

• Parallel computer models
• Speedup and performance
• Multiprocessors and multi-computers
• Simultaneous multithreading architectures
• Interconnection structures
• Cache coherence

Sample Exams

Architecture: January 2002, January 1997