Founded in 1966

PhD Proposal

Synchronization Point Driven Characterization and Resource Management for Shared-Memory Applications

Socrates Demetriades

Friday April 13, 2012
12:00 pm - Sennott Square 6106 - Eli Lilly Room

Abstract

With the proliferation of Chip Multiprocessors (CMPs), shared memory applications are becoming increasingly popular, expanding fast in every application domain. Those applications exhibit dynamic behaviors that go beyond traditional observations made for single threaded applications, further affected by the data sharing and communication. To ensure that next generation CMPs will perform well on their anticipated workloads, it is vital to employ techniques that can dynamically track and understand the particular behaviors of the shared memory applications, and effectively guide resource management mechanisms.

This work proposes a new approach for shared-memory program characterization and resource management, driven by the software synchronization constructs that exist in those applications. The hypothesis is that, the type, the position, and the execution of synchronization constructs inherently encompass information that, if exposed to the hardware, can aid in various ways the management of system resources. In contrast to the traditional hardware or hardware/software based approaches, the synchronization point based resource management framework is neither blind to the application's possible inherent characteristics, nor subject to programmer's intervention.

The goal is to provide a simple, lightweight, yet effective framework for tracking the varying program behavior and guiding dynamic optimizations. First, various aspects of the program behavior (e.g., throughput, bandwidth, communication, contention) are characterized in relation to the synchronization points and certain relations are identified and extracted. Then the feasibility of guiding resource management techniques using synchronization points is examined, and possible optimizations are evaluated. Those include exploiting performance/power trade-off in the on-chip interconnect, coherence communication prediction, and synchronization point driven scheduling in heterogeneous architectures.

Dissertation Adviser

Sangyeun Cho, Department of Computer Science

Committee Members

Dr. Bruce Childers, Department of Computer Science
Dr. Rami Melhem, Department of Computer Science
Dr. Alex Jones, Department of Electrical and Computer Engineering

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