PhD Proposal

Analytical Models for Chip Multiprocessor Memory Hierarchy Design and Management

Taecheol Oh

Friday November 20, 2009
10:00 am - SENSQ 6106 Eli Lilly Room

Abstract

Continued advances in circuit integration technology has ushered in the era of chip multiprocessor (CMP) architectures as further scaling of the performance of conventional wide-issue superscalar architectures remains difficult and expensive.
CMP architectures take advantage of Moore's Law by integrating more cores in a given chip area rather than a single fast yet larger core, and typically achieve higher performance with multithreaded workloads.
However, CMP architectures pose many new memory hierarchy design and management problems that must be considered.
For example, how many cores and how much cache must we integrate in a single chip to obtain the best throughput possible?
Which is more cost-effective, putting more cache space or increasing the memory bandwidth?
Would explicit memory bank allocation among co-scheduled processes bring benefits or losses?
This thesis research proposes to develop a series of simple yet powerful analytical models to study new memory hierarchy design and management problems for CMPs.
Since the CMP design space is large and simulating only one design point of the design space under various workloads would be extremely time-consuming, the conventional simulation-based research approach quickly becomes ineffective.
We anticipate that our analytical models will provide practical tools with which CMP designers can correctly guide their design efforts in an early design stage by better understanding potentially complex interactions among key design parameters.

Dissertation Adviser

Dr. Sangyeun Cho, Department of Computer Science

Committee Members

Rami Melhem, Ph.D., Department of Computer Science,
Jun Yang, Ph.D., Department of Electrical and Computer Engineering,
Youtao Zhang, Ph.D., Department of Computer Science