Reconfigurable Computing Machines: Architectures, Systems, and Applications
Duncan Buell
Monday, November 8, 2004
10:00am - SENSQ 5317/19
9:30am coffee and pastries
Abstract
The use of Field Programmable Gate Arrays (FPGAs) for computing in hybrid computer architectures and on applications not well suited to traditional processor architectures is now several years old, but fundamental problems have continued to plague those who would use such machines for computation. At the heart of the problem is and always has been that implementing an application has been a "hardware design" process and not a "programming" process.
It now appears, however, that programming of a commercial reconfigurable computer is possible. We will describe the implementation of the DARPA High Productivity Computing Systems Discrete Mathematics Benchmarks on the SRC Computers SRC-6. In most instances, these benchmarks can be programmed in C, debugged, and optimized using techniques that are familiar to programmers of high-end machines. In the few instances in which the compiler tools have proven insufficient, hardware design methods and tools are used to implement libraries and functions called by the C program. The effectiveness of the SRC-6 is still limited due to hardware constraints, but because we can now readily program applications, we are able to explore fully the parameters of memory bandwidth, space/time tradeoff in the use of silicon, and the hardware/software codesign issues of balancing computation on the host processor versus computation on the FPGAs.
Bio
Duncan A. Buell received the B. S. and M. A. degrees in mathematics from the University of Arizona and University of Michigan, respectively, and in 1976 his Ph. D. in mathematics from the University of Illinois at Chicago. He was an assistant and then associate professor in the Department of Computer Science at Louisiana State University in Baton Rouge.
In 1986 he joined the Supercomputing Research Center (now the Center for Computing Sciences), a division of the Institute for Defense Analyses, doing high performance computing and computational mathematics research for the National Security Agency. He has written two books and more than fifty research papers in number theory, document and information retrieval, parallel algorithms, and computer architecture.
While at IDA he was project manager for the Splash 2 reconfigurable computing project, one of the first successful ventures into the use of Field Programmable Gate Arrays (FPGAs) as the programmable "CPU" in what is now known as a reconfigurable a computing machine. He was also one of the co-founders of the FPGAs for Custom Computing Machines (FCCM) conference held yearly since 1993.
In 1997 Dr. Buell was a member of team that received a National Meritorious Unit Citation from Director of Central Intelligence George Tenet for the solution of a long-outstanding problem of national significance.
He joined the University of South Carolina as Professor and Chair of the Department of Computer Science and Engineering in October 2000, where he continues research in high performance and reconfigurable computing.