Inductive Noise at the Microarchitectural Level: Analysis Techniques and Effective Solutions
Russ Joseph
Princeton University
Friday, March 19, 2004
10:00am - SENSQ 5317
Refreshments at 9:30am in SENSQ 5319
Abstract
Inductive noise on microprocessor power lines, known more commonly as the dI/dt problem, can degrade the performance and reliability of a CPU. While aggressive power saving techniques such as clock gating can reduce average power consumption, they unfortunately increase the variability of current drawn by the processor. This leads to increased inductive power supply noise, which can cause circuits to fail. Although microarchitectural policies promote the problematic current variations, traditional methods of coping with inductive noise focus on electronic packaging techniques. Given recent industry trends, these increasingly expensive packaging approaches may not adequately solve the dI/dt problem in future processors.
This talk examines the dI/dt problem at the microarchitectural, and introduces novel techniques to characterize and reduce the effects of inductive noise. The effect that clock-gating and other power-saving techniques have on inductive noise makes microarchitectural analysis a natural option.
The material presented in this talk applies theory from other branches of electrical engineering to address two problems related to inductive noise: dI/dt workload characterization and microarchitectural voltage regulation. While microarchitecture studies do not commonly incorporate frequency-based analysis, the frequency sensitive nature of inductive noise makes wavelet analysis an effective tool for dI/dt characterization of programs. This talk also presents a strategy for applying control theory to the design of microarchitectural voltage regulation mechanisms. These controllers make pipeline and instruction scheduling decisions that prevent dangerous power supply fluctuations, decreasing the burden on the electronic packaging, and ultimately helping to reduce cost and complexity.
Biosketch
Russ Joseph is currently a Ph.D. candidate in Electrical Engineering at Princeton University. His research focuses on power constraints for high-performance processors at the microarchitectural level. In particular, some of his recent work has explored techniques to characterize and mitigate inductive noise variations, known more commonly as the dI/dt problem.
Prior to his graduate studies at Princeton, Russ attended Carnegie Mellon University. In 1995, he earned a B.S. in Electrical and Computer Engineering (with Double Major in Computer Science) from CMU. He is the recipient of an IBM Graduate Fellowship Award.