Tutorial Overview (December 4, 2011, 1:30 PM - 5:00 PM)

DRAM by itself can no longer satisfy the never-ending demand for more main memory space. In many computer systems, especially ones that execute data-intensive applications, DRAM is quickly becoming a poor choice due to its high energy consumption, susceptibility to single-event upset errors, and poor density. To address the challenges of DRAM, there is has been a large and recent wave of newly proposed memory architectures based on persistent random-access memory (PRAM) technologies. These new architectures will be hybrids that use multiple technologies. Currently, the most promising combination is a small DRAM with a large phase-change memory (PCM). Hybrid memory architectures could have a dramatic impact on future computer systems, including their latency, energy, and reliability.

This tutorial will cover hybrid main memory architectures, especially ones that use DRAM and PCM. The tutorial aims to prepare MICRO attendees to both use and perform research on architecture and software aspects of hybrid memory systems. Unlike recent PCM tutorials, our focus will be the architecture for hybrid memories, including discussion of many very recent pro- posals. The tutorial topics will include an introduction to PRAM, promising memory architectures that incorporate PCM and DRAM, handling asymmetric read/write latency and write energy and endurance problems of using PCM in main memory, and the impact on system of a hybrid memory.

The tutorial will describe a flexible and accurate simulation infrastructure for studying architectural aspects of DRAM+PCM hybrid memories. This simulator will form an important focus of the tutorial. The tutorial will describe the simulator's operation and how it can be used and extended for research on open problems about DRAM+PCM main memory. To illustrate the simulator, two case studies will be described. One study will examine how the configuration of a hybrid memory system can lead to drastically differing performance and energy results. Another case study will examine the influence of read/write queueing and associated policies on performance and endurance.